1. Field of the Invention
This invention relates to the field of semiconductor processing and MOS transistors and, more particularly, to a structure and method in which source/drain regions within the semiconductor substrate are detached or laterally displaced from the transistor gate.
2. Description of the Relevant Art
The operating characteristics of transistors fabricated with metal-oxide-semiconductor (MOS) integrated circuit techniques are a function of the transistor""s dimensions. In particular, the source-to-drain current (Ids) is proportional to the ratio of the transistor""s width (W) to the transistor""s length (L). For given a transistor width and a given biasing condition (e.g., VG=3V, VD=3V, and Vs=0V), Ids is maximized by minimizing the transistor length L. Minimizing transistor channel length also improves the speed of integrated circuits comprised of a large number of individual transistors because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Minimizing L is, therefore, desirable from an device operation standpoint. In addition, minimizing the transistor length L is desirable from a manufacturing perspective because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases and with it, a corresponding increase in the circuit complexity that can be achieved on the given area of silicon.
The benefits achieved by minimizing the channel length L are accompanied by an increased sensitivity to voltage breakdown. As device channel lengths drop below 0.5 microns, the stability and reliability of the transistor must be carefully monitored. One widely recognized and easily tested parameter is the drain voltage breakdown (commonly referred to as BVDSS). BVDSS can be measured by grounding the gate, source, and substrate of a test transistor and ramping the drain voltage from 0 volts while measuring the drain voltage at which a drain current of approximately 1xcexcA begins to conduct. BVDSS, therefore, indicates a drain voltage at which the device conducts current whether or not a bias is applied to the transistor gate. Because unwanted drain currents increase the power requirements of the integrated circuit and the temperature of the integrated circuit, and can result in an inadvertent activation of other transistors within the circuit, the maximization of BVDSS is critical, especially in short channel devices. In conventional MOS transistors, BVDSS begins to approach the operating voltage of the transistor as the channel length falls below approximately 0.5 microns. FIG. 1 shows a transistor 10 which is comprised of a substrate 12, a gate dielectric 14, a gate electrode 16, and a pair of source/drain regions 20a and 20b. Transistor 10 is fabricated such that channel boundaries 22a and 22b of source/drain regions 20a and 20b are in close proximity to lateral positions of first and second sidewalls 18a and 18b of gate electrode 16. Source/drain regions 20a and 20b are typically heavily doped with an impurity to provide a plentiful source of mobile carriers for conduction after an inversion region is created in the substrate 12 under gate electrode 16. The use of heavily doped source/drain regions that have a channel boundary coincident with sidewalls of the transistor gate results in a transistor having an undesirably low drain breakdown voltage BVDSS. BVDSS decreases with channel length L partly because the maximum electric field within channel region 21 of transistor 10 increases. This increased electric field can provide sufficient energy to mobile carriers within drain region 20b to overcome the reversed biased junction between drain region 20b and channel region 21 thereby increasing the drain current.
One well known approach to reduce the short channel effects described in the preceding paragraph includes the fabrication of lightly doped drain (LDD) structures. FIG. 2 shows a typical transistor 30 incorporating LDD regions 40a and 40b. Transistor 30 includes a semiconductor substrate 32, a gate dielectric 34, a gate electrode 36, lightly doped regions 40a and 40b, and heavily doped regions 48a and 48b. Transistor 30 also includes spacer structures 44a and 44b that facilitate the lateral displacement of the heavily doped regions 48a and 48b from sidewalls 38a and 38b of gate electrode 36. Typically, the peak impurity concentration within lightly doped drain regions 40a and 40b is less than the peak impurity concentration within heavily doped regions 48a and 48b. Channel boundaries 42a and 42b of lightly doped regions 40a and 40b are approximately aligned with lateral positions of first sidewall 38a and second sidewall 38b of gate electrode 36. Interior boundaries 49a and 49b of heavily doped regions 48a and 48b are laterally displaced from sidewalls 38a and 38b of gate electrode 36. Because lightly doped regions 40a and 40b are typically doped with a lighter impurity concentration than heavily doped regions 48a and 48b, the resistivity of lightly doped regions 40a and 40b is higher than a resistivity of heavily doped regions. Accordingly, an applied drain voltage is distributed across lightly doped drain region 40b and results in reduced electric field within channel region 41 that results in an increased BVDSS of transistor 30. It will be appreciated that in the case of both transistor 10 of FIG. 1 and transistor 30 of FIG. 2, the channel boundaries of the source/drain impurity distributions are approximately coincident with sidewalls of the gate electrode. This alignment of the source/drain boundaries and the gate electrode sidewalls has generally been considered desirable. Significant overlap between the gate electrode and the source/drain regions is avoided because of the increased parasitic capacitance that results when a source/drain region extends significantly below the gate electrode. Because the transistor drain typically functions as the device output and the gate electrode typically functions as the device input, any parasitic capacitance between drain and gate produces an undesirable feedback mechanism that limits the high frequency operation of the device. See, e.g., Ben G. Streetman, Solid State Electronic Devices 319-321(Prentice-Hall 1980). Therefore, conventional transistors have generally been fabricated in a manner designed to minimize overlap between the source/drain regions and the gate electrode, most notably through the use of the self aligned silicon gate technology. Despite the desire to minimize parasitic capacitance due to excessive overlap, conventional transistor design typically required some lateral overlap between the source/drain regions and the gate electrode. The overlap was generally considered necessary to form a complete channel from source to drain region and it was believed that a non-functional device could result if the gate did not extend to the source and drain impurity distributions. Id.
The requirement that the gate electrode extend to the source and drain impurity distributions results in an undesirably low BVDSS when the channel length of the transistor drops below 0.5 microns. This undesirable result can only be partially offset by implementation of the LDD structures described with respect to FIG. 2. The presence of lightly doped drain structures does not fully restore the BVDSS of the transistor to a desired range. (It is generally considered desirable to have BVDSS at least 1.5 to 3 times greater than the normal operating voltage of the particular technology). As discussed previously, short channel devices are desirable because of the larger number of such devices that can be fabricated within a given area. Therefore, it is highly desirable to design and fabricate a semiconductor structure and process resulting in transistors having increased tolerance to BVDSS for channel lengths well below 0.5 microns.
The problems identified above are in large part addressed by transistors and integrated circuits fabricated according to a semiconductor manufacturing process in which the drain region is laterally displaced from a sidewall of the conductive gate. In alternative embodiments, the source region may also be displaced from the lateral position of the conductive gate. Displacing the drain region and, in some cases the source region, increases the transistor""s tolerance to BVDSS and permits the fabrication of deep submicron channel transistor, exhibiting uncharacteristically high breakdown voltages. Specific embodiments may take on a variety of forms as discussed in greater detail below. In addition, these detached drain transistors may be integrated into a conventional transistor fabrication process to produce devices and integrated circuits including both detached drain and more conventional transistors. In this manner, desired devices may be selectively fabricated to exhibit a higher BVDSS while the remaining transistors are fabricated according to a more conventional design and process flow.
Broadly speaking, the present invention, in a first implementation, comprises a detached drain transistor. The detached drain transistor includes a semiconductor substrate, a source impurity distribution, a drain impurity distribution, a gate dielectric, and a conductive gate. The source impurity distribution is substantially contained within a source region of the semiconductor substrate. The drain impurity distribution is substantially contained within a detached drain region of the semiconductor substrate. The gate dielectric is formed on an upper surface of the semiconductor substrate. The conductive gate is formed on the gate dielectric and laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between the source region of the semiconductor substrate and the detached drain region. The channel boundary of the detached drain region is laterally displaced from a first sidewall of the conductive gate by a detached displacement.
Preferably, the semiconductor substrate comprises single crystal silicon having a resistivity of approximately 10 to 15xcexa9-cm. In one embodiment, the source region includes a lightly doped source region and a heavily doped source region. The lightly doped source region extends to a first depth below the upper surface of the semiconductor substrate and is laterally displaced within the substrate such that a channel boundary of the lightly doped source region is approximately coincident with a lateral position of a second sidewall of a conductive gate. The heavily doped source region extends to a second depth below the upper surface of the substrate. The second depth is greater than the first depth and the heavily doped source region is laterally displaced within the semiconductor substrate such that an interior boundary of the heavily doped source region is displaced from the second sidewall of the conductive gate by a source displacement. In this embodiment, the source impurity distribution includes a first source impurity distribution substantially contained within the lightly doped source region and a second source impurity distribution substantially contained within the heavily doped source region. A peak concentration of the second source impurity distribution is preferably greater than a peak concentration of the first impurity distribution. Preferably, a peak concentration of the drain impurity distribution is approximately equal to a peak concentration of the second source impurity distribution and the drain displacement is approximately equal to the source displacement.
Preferably, the gate dielectric is a thermal oxide having a thickness of approximately 20 to 200 angstroms. The conductive gate preferably comprises polysilicon having a sheet resistivity of less than approximately 500xcexa9/square. Alternatively, the conductive gate may comprise a metal of aluminum, copper, tungsten or alloys thereof. The lateral dimension of the conductive gate is ideally less than approximately 0.3 microns, while the drain displacement, in this embodiment, is approximately 500 to 1500 angstroms.
The present invention still further contemplates a semiconductor manufacturing process. The process includes the steps of providing a semiconductor substrate, forming a gate dielectric on an upper surface of the semiconductor substrate, forming a conductive gate on the gate dielectric, introducing a source impurity distribution into a source region of the semiconductor substrate, and introducing a drain impurity distribution into a detached drain region. The semiconductor substrate includes a channel region that is laterally disposed between the source region and the detached drain region of the semiconductor substrate. The conductive gate is formed such that a first sidewall of the conductive gate is laterally displaced a drain displacement from a channel boundary of the detached drain region and further such that a lateral position of a second sidewall of the conductive gate is approximately coincident with a lateral position of a channel boundary of the source region of the semiconductor substrate. The drain impurity distribution is introduced into the detached drain region of the semiconductor substrate whereby the drain impurity distribution is laterally displaced from the first sidewall of the conductive gate by the drain displacement.
The step of forming the gate dielectric preferably comprises thermally oxidizing the upper surface of the semiconductor substrate at a temp of greater than approximately 800xc2x0 C. to form a thermal oxide of approximately 20 to 200 angstroms in thickness. The conductive gate may be formed by depositing a conductive film on the gate dielectric and patterning the conductive film with a photolithography masking step. In one embodiment, the deposition of the conductive film comprises chemically vapor depositing polysilicon and introducing a gate impurity distribution into the polysilicon to reduce the sheet resistivity of the polysilicon to less than approximately 500xcexa9/square. In an alternative embodiment, the step of depositing the conductive film comprises sputter depositing a metal selected from a group consisting of aluminum, copper, tungsten, and alloys thereof. The source region, in one embodiment, includes a lightly doped source region and a heavily doped source region. In this embodiment, the step of introducing the source impurity distribution into the source region comprises ion implanting a first source impurity distribution into the semiconductor substrate, forming a spacer structure on the second sidewall of the conductive gate, and ion implanting a second source impurity distribution into the semiconductor substrate. In this embodiment, the first source impurity distribution is ion implanted into the lightly doped impurity region of the semiconductor substrate such that the lightly doped impurity region substantially contains the first source impurity distribution. The lightly doped impurity region extends to a first depth below the upper surface of the semiconductor substrate. The spacer structure is formed on the second sidewall of the conductive gate such that the spacer structure protects a portion of the source region proximal to the second sidewall. The second source impurity distribution is implanted into the semiconductor substrate such that the heavily doped impurity region substantially contains the second source impurity distribution and wherein the heavily doped impurity region extends to a second depth below the upper surface of the semiconductor substrate. The first depth is less than the second depth and a peak concentration of the first source impurity distribution is less than a peak concentration of the second source impurity distribution. Preferably, the step of introducing a drain impurity distribution includes forming a spacer structure on the first sidewall of the conductive gate. Ideally, the lateral dimension of the spacer structure is approximately equal to the drain displacement such that the first spacer structure protects a portion of the channel region laterally displaced between the channel boundary of the detached drain region and a lateral position of the first sidewall of the conductive gate. The drain displacement is preferably less than approximately 0.15 microns. Preferably, the steps of introducing the impurity distributions into the semiconductor substrate is comprised implanting ions of arsenic, boron or phosphorous into the semiconductor substrate. In one such embodiment, an implant dose for the step of introducing the drain impurity distribution is in the range of approximately 2xc3x971012 to 5xc3x971015 atoms/cm2.
In a second implementation, the present invention still further contemplates an alternative embodiment of the detached drain transistor comprising a semiconductor substrate, a gate dielectric, and a first and a second source/drain impurity distribution. The substrate includes a channel region laterally displaced between a first and a second source/drain region. The gate dielectric is formed on an upper surface of the semiconductor substrate. The conductive gate is formed on the gate dielectric and includes a first and a second sidewall. The first and second sidewalls of the conductive gate are laterally displaced from channel boundaries of the first and second source/drain regions by a source/drain displacement. The first and second source/drain impurity distributions are substantially contained within the first and second source/drain regions respectively of the semiconductor substrate. Preferably, the transistor further includes a gate insulator formed in contact with the first and second sidewalls of the semiconductor substrate. Respective exterior sidewalls of the gate insulator are laterally displaced from the first and second sidewalls by a first displacement. In one embodiment, the gate insulator includes an inner insulator comprising a first dielectric material and an outer insulator comprising a second insulator material. In one such embodiment, the inner insulator comprises oxide and the outer insulator comprises silicon nitride. In one embodiment, a thickness of the inner insulator is approximately 50 to 100 angstroms and a thickness of the outer insulator is less than or equal to approximately 200 angstroms. The gate dielectric typically comprises an oxide having a thickness of approximately 20 to 200 angstroms while the conductive gate may comprise polysilicon having a sheet resistivity of less than approximately 500xcexa9/square or, alternatively, the conductive gate may comprise aluminum, copper, tungsten or alloys thereof. A lateral dimension of the conductive gate is preferably less than 0.3 microns and the breakdown voltage of the transistor is greater than approximately 7 volts. Preferably, the first and second source/drain impurity distributions comprise ions of arsenic, phosphorous or boron and a peak concentration of the first and second source/drain impurity distributions is preferably greater than 1xc3x971019 atoms/cm3. In one embodiment, the source/drain displacement is approximately 200 to 300 angstroms.
Embodiments of the present invention still further contemplate an integrated circuit. The integrated circuit comprises a semiconductor substrate that includes a first transistor region and second transistor region laterally displaced from the first transistor region. The integrated circuit further includes a first transistor formed over the first transistor region and second transistor formed over the second transistor region. The first transistor is formed according to the transistor of the previous paragraph. The second transistor includes a second conductive gate, a pair of lightly doped impurity distributions, and a pair of heavily doped impurity distributions. The pair of lightly doped impurity distributions are substantially contained within a pair of lightly doped impurity regions laterally displaced on either side of a channel region of the second transistor region. The channel boundaries of the lightly doped regions are approximately coincident with lateral positions of the first and second sidewalls of the second conductive gate. A peak concentration of the lightly doped impurity distributions is less than approximately 5xc3x971017 atoms/cm3. The pair of heavily doped impurity distributions are substantially contained within a pair of heavily doped impurity regions laterally displaced on either side of the channel region of the second transistor. Interior boundaries of the heavily doped regions are laterally displaced from the first and second sidewalls of the second conductive gate by approximately the source/drain displacement of the first transistor. A peak concentration of the heavily doped impurity distributions is greater than approximately 1xc3x971019 atoms/cm3.
The present invention still further contemplates a second implementation of a semiconductor process. The process includes providing a semiconductor substrate, forming a gate dielectric on the semiconductor substrate, forming a conductive gate, and introducing first and second impurity distributions into the semiconductor substrate. The semiconductor substrate includes a channel region laterally displaced between a first and second source/drain region. The conductive gate is formed on an upper surface of the gate dielectric such that first and second sidewalls of the conductive gate are laterally displaced from respective channel boundaries of the first and second source/drain regions by a source/drain displacement such that a displacement between the channel boundaries is greater than a lateral dimension of the conductive gate. Thereafter, first and second impurity distributions are introduced into the semiconductor substrate such that the first and second source/drain regions substantially contain the respective impurity distributions. Preferably the step of forming the gate dielectric comprises thermally oxidizing the upper surface of semiconductor substrate at a temperature greater than approximately 800xc2x0 C. for a duration sufficient such that a thickness of the gate dielectric is approximately 20 to 200 angstroms. In one embodiment, the process further comprises prior to the step of introducing the first and second impurity distributions, thermally oxidizing the conductive gate to form an inner gate insulator in contact with the first and second sidewalls of the conductive gate and wherein the thickness of the inner gate insulator is approximately 50 to 100 angstroms. Subsequently, a second gate insulator is preferably formed on the exterior sidewalls of the inner gate insulator. A preferred thickness of the second gate insulator is approximately 150 to 250 angstroms. Ideally, the second gate insulator is formed by depositing silicon nitride upon the topography defined by the first gate insulator and the upper surface of the semiconductor substrate and anisotropically etching the silicon nitride layer to remove portions of the silicon nitride substantially parallel to the upper surface of the semiconductor substrate whereby the second gate insulator comprises spacer structures in contact with exterior sidewalls of the inner gate insulator.
In a third implementation, the present invention still further contemplates an integrated circuit comprising a semiconductor substrate, a gate dielectric formed on an upper surface of the semiconductor substrate, a first and a second conductive gate formed on the gate dielectric, a lightly doped impurity distribution, and a first source impurity distribution, and a detached impurity distribution. The first and second conductive gates are formed on the gate dielectric such that the first conductive gate is displaced over a first transistor region of the semiconductor substrate and the second transistor gate is displaced over a second transistor region of the semiconductor substrate. The lightly doped impurity distribution is introduced into the second transistor region such that it is substantially contained within first and second lightly doped impurity regions laterally displaced on either side of a channel region of the second transistor region. A lateral dimension of the channel region of the second transistor region is approximately equal to a lateral dimension of the second conductive gate such that channel boundaries of the first and second lightly doped impurity regions are approximately coincident with lateral positions of the first and second sidewalls of the second conductive gate. The first source impurity distribution is substantially contained within a first source region of the first transistor region. The first source region is laterally displaced from a channel region of the first transistor region. A channel boundary of the first source region is approximately coincident with a lateral position of the second sidewall of the first conductive gate. The detached impurity distribution is substantially contained within first and second pairs of detached source/drain regions. Respective pairs of the detached source/drain regions are laterally displaced on either side of channel regions within corresponding transistor regions. Interior boundaries of the detached source/drain regions are laterally displaced a source/drain displacement from respective sidewalls of the conductive gate. Preferably, the integrated circuit further includes a first and a second pair of spacer structures formed in contact with sidewalls of the first and second conductive gates respectively. A lateral dimension of the spacer structures is approximately equal to the source/drain displacement. In one embodiment, a lateral dimension of the spacer structure is approximately 500 to 1000 angstroms. Preferably, the first conductive gate has a lateral dimension less than approximately 0.3 microns. In alternative embodiments, the first and second conductive gates may comprise polysilicon having a sheet resistivity less than approximately 500xcexa9/square or the conductive gates may comprise a metal such as aluminum, copper, tungsten or alloys thereof.
The present invention still further contemplates a third implementation of an integrated circuit process comprising providing a semiconductor substrate, forming a gate dielectric on an upper surface of the semiconductor substrate, forming first and second conductive gates on the gate dielectric, introducing a lightly doped impurity distribution into the substrate, introducing a first source impurity distribution into the substrate, and introducing a detached impurity distribution into the semiconductor substrate. The first and second conductive gates are formed on the gate dielectric such that the first conductive gate is displaced over a first transistor region of the semiconductor substrate and the second transistor gate is displaced over a second transistor region of the semiconductor substrate, the first transistor region being laterally displaced from the second transistor region. The lightly doped impurity distribution is introduced into the second transistor region of the semiconductor substrate such that the lightly doped impurity distribution is substantially contained within first and second lightly doped impurity regions laterally displaced on either side of a channel region of the second transistor region. A lateral dimension of the channel region of the second transistor region is approximately equal to a lateral dimension of the second conductive gate. The first source impurity distribution is introduced into the semiconductor substrate such that it is substantially contained within a first source region of the first transistor region. The first source region is laterally displaced from a channel region of the. first transistor region such that a channel boundary of the first source region is approximately coincident with a second sidewall of the first conductive gate. The detached impurity distribution is introduced into the semiconductor substrate such that it is substantially contained within first and second pairs of detached source/drain regions. Respective pairs of the detached source/drain regions are laterally displaced on either side of channel regions within corresponding transistor regions of the semiconductor substrate. Interior boundaries of the detached source/drain regions are laterally displaced from respective sidewalls of respective conductive gates by a source/drain displacement.
Preferably, the step of introducing the lightly doped impurity distribution includes implanting ions of arsenic, boron, or phosphorous at an implant energy less than approximately 20 keV and at a dose of less than approximately 5xc3x971014 atoms/cm2. The step of introducing the first source impurity distribution comprises implanting ions of arsenic, boron, or phosphorous at an implant dose in the approximate range of 2xc3x971012 to 1xc3x971015 atoms/cm2. The step of introducing the detached impurity distribution includes implanting ions of arsenic, boron or phosphorous using an implant dose greater than approximately 5xc3x971014 atoms/cm2. In one embodiment, the process further includes, prior to introducing the detached impurity distribution, forming a first pair and a second pair of spacer structures on sidewalls of the first and second conductive gates respectively. A lateral dimension of the spacer structures is approximately equal to the source/drain displacement.
In a fourth implementation, the present invention still further contemplates a detached drain transistor including a semiconductor substrate, a gate dielectric formed on an upper surface of the substrate, a conductive gate formed on the gate dielectric, a first pair of spacer structures, a first source impurity distribution, a second pair of spacer structures, and a drain impurity distribution. The conductive gate is laterally disposed over a channel region of the semiconductor substrate. The channel region extends laterally between a first source region of the semiconductor substrate and a detached drain region of the semiconductor substrate. A channel boundary of the detached region is laterally displaced from a first sidewall of the conductive gate by a drain displacement. A channel boundary of the first source region is laterally displaced from a second sidewall of the conductive gate by a source displacement. The first pair of spacer structures is formed in contact with the first and second sidewalls of the conductive gate. A lateral dimension of the first pair of spacer structures is approximately equal to the source displacement. The first source impurity distribution is substantially contained within the first source region of the semiconductor substrate. The second pair of spacer structures is formed on exterior sidewalls of the first pair of spacer structures such that exterior sidewalls of the second pair of spacer structures are displaced from respective sidewalls of the conductive gate by approximately said drain displacement. The drain impurity distribution is substantially contained within the detached drain region of the semiconductor substrate. Preferably, a lateral dimension of the conductive gate is less than approximately 0.3 microns and the breakdown voltage of the transistor is greater than approximately 7 volts. In a presently preferred embodiment, the source displacement is approximately 50 to 400 angstroms while the drain displacement is approximately 500 to 1500 angstroms. In one embodiment, the first pair of spacer structures comprises silicon nitride. The first source impurity distribution preferably includes ions of arsenic, boron, or phosphorous and has a peak concentration in the approximate range of 1xc3x971017 to 5xc3x971020 atoms/cm3. In one embodiment, the transistor further includes a second source impurity distribution substantially contained within a second source region of the semiconductor substrate. An interior boundary of the second source region is laterally displaced from the second sidewall of the conductive gate by approximately said drain displacement. A peak concentration of the second source impurity distribution is approximately equal to a peak concentration of the drain impurity distribution such that the second source impurity distribution represents a mirror image of the drain impurity distribution. In one embodiment, the second pair of spacer structures is comprised of oxide.
In a fifth implementation, the present invention still further contemplates a semiconductor manufacturing process comprising providing a semiconductor substrate, forming a gate dielectric on an upper surface of the semiconductor substrate, forming a conductive gate on an upper surface of the gate dielectric, forming a first pair of spacer structures on the first and second sidewalls of the conductive gate, introducing a first source impurity distribution into the semiconductor substrate, forming a second pair of spacer structures on respective exterior sidewalls of the first pair of spacer structures, and introducing a drain impurity distribution into the detached drain region of the semiconductor substrate. The semiconductor substrate includes a channel region laterally displaced between a first source region and a detached drain region. The conductive gate is formed on the gate dielectric such that the conductive gate includes a first and a second sidewall. The first pair of spacer structures is formed on the sidewalls of the conductive gate such that exterior sidewalls of the first pair of spacer structures are displaced from the first and second sidewalls of the conductive gate by a source displacement. The first impurity distribution is introduced into the first source region of the semiconductor substrate wherein a channel boundary of the first source region is laterally displaced from the second sidewall of the conductive gate by the source displacement. The first source region extends to a first source depth below the upper surface of the semiconductor substrate. The formation of the second pair of spacer structures on the exterior sidewalls of the first pair of spacer structures is accomplished such that exterior sidewalls of the second pair of spacer structures are laterally displaced from the first and second sidewalls of the conductive gate by a drain displacement. The introduction of the drain impurity distribution into the detached drain region of the substrate is accomplished such that a channel boundary of the detached drain region is laterally displaced from the first sidewall of the conductive gate by the drain displacement. The conductive gate may comprise heavily doped CVD polysilicon or, alternatively, the conductive gate may be formed from a metal such as aluminum, copper, tungsten, or alloys thereof. In one embodiment, the process of forming the first pair of spacer structures includes chemically vapor depositing a substantially conformal first dielectric layer on the topography cooperatively defined by the conductive gate and the upper surface of the semiconductor substrate. The conformal deposition of the first dielectric layer in this embodiment is preferably carried out at a pressure less than approximately 2 torrs. The first dielectric layer is then anisotropically etched to remove portions of the first dielectric layer over portions of the topography that are substantially parallel with the upper surface of the semiconductor substrate. In one presently preferred embodiment, the first dielectric layer comprises silicon nitride. In one embodiment, the process of forming the second pair of spacer structures includes chemically vapor depositing a substantially conformal second dielectric layer on the topography cooperatively defined the conductive gate and the upper surface of the semiconductor substrate. Thereafter, the second dielectric layer is anisotropically etched to remove portions of the second dielectric layer above portions of the topography that are substantially parallel with the upper surface of the semiconductor substrate.
The present invention still further contemplates an integrated circuit comprising a semiconductor substrate, a gate dielectric formed on an upper surface of the semiconductor substrate, first and second conductive gates, first and second gate insulators, a lightly doped impurity distribution, a first source/drain impurity distribution, and a second source/drain impurity distribution. The semiconductor substrate includes a first transistor region laterally displaced from a second transistor region. The first and second conductive gates are formed on the gate dielectric over the first and second transistor regions respectively. The conductive gates each include a first and a second sidewall. The first and second gate insulators are formed in contact with the sidewalls of the first and second conductive gates, respectively. The lightly doped impurity distribution is substantially contained within lightly doped source/drain regions laterally displaced on either side of the channel region of the second transistor region. The channel boundaries of the lightly doped source/drain regions are approximately coincident with the lateral position of the first and second sidewalls of the second conductive gate. The first source/drain impurity distribution is substantially contained within first source/drain regions that are laterally displaced on either side of a channel region of the first transistor region. The channel boundaries of the first source/drain impurity distribution are laterally displaced from the first and second sidewalls of the first conductive gate by a first displacement. The second source/drain impurity distribution is substantially contained within the second source/drain regions of the first transistor region. The interior boundaries of the second source/drain regions are laterally displaced from first and second sidewalls of the first conductive gate by a second displacement. The second displacement is greater than the first displacement. Preferably, the first and second gate insulators comprise oxide and a thickness of the gate insulators is approximately 50 to 100 angstroms. The lightly doped impurity distribution preferably includes ions of arsenic, boron, or phosphorous having a peak concentration less than approximately 5xc3x971017 atoms/cm3. A peak concentration of the first source/drain impurity distribution is preferably in the range of approximately 1xc3x971017 to 5xc3x971020 atoms/cm3. A peak concentration of the second source/drain impurity distribution is preferably greater than approximately 1xc3x971019 atoms/cm3. The first displacement is preferably in the range of approximately 100 to 300 angstroms. The second displacement is ideally greater than the first displacement and the second displacement is in the range of approximately 200 to 400 angstroms. In a preferred embodiment, the lateral dimension of the first conductive gate is less than approximately 0.3 microns and the breakdown voltage of the first transistor is greater than approximately 7 volts.
The present invention still further contemplates an integrated circuit manufacturing process comprising providing a semiconductor substrate, forming a gate dielectric on an upper surface of the semiconductor substrate, forming a first and a second conductive gate on the gate dielectric, introducing a lightly doped impurity distribution into the semiconductor substrate, forming a first and a second gate insulator, forming a first pair of dielectric spacers, introducing a first source/drain impurity distribution into the semiconductor substrate, removing the first pair of spacer structures, forming a second pair of spacer structures, and introducing a second source/drain impurity distribution into the semiconductor substrate. The semiconductor substrate includes a first transistor region laterally displaced from a second transistor region. The first and second conductive gates are formed over the first and second transistor regions respectively of the semiconductor substrate. The first and second conductive gates each include a first and second sidewall. The lightly doped impurity distribution is introduced into a first and a second lightly doped impurity region. The first and second lightly doped impurity regions are laterally displaced on either side of a channel region of the second transistor region. The channel boundaries of the first and second lightly doped impurity distributions are approximately coincident with lateral positions of the first and second sidewalls of the second conductive gate. The first and second gate insulators are formed in contact with the sidewalls of the first and second conductive gates respectively. The first pair of dielectric spacers are formed on exterior sidewalls of the first gate insulator such that exterior sidewalls of the first pair of spacer structures are laterally displaced from first and second sidewalls respectively of the conductive gate by a first displacement distance. The first source/drain impurity distribution is introduced into a pair of first source/drain regions. The first pair of source/drain regions are laterally displaced on either side of a channel region of the first transistor region. The channel boundaries of the first and second source/drain regions are laterally displaced from the first and second sidewalls of the first conductive gate by the first displacement distance. The second pair of spacer structures are formed on exterior sidewalls of the first gate insulator such that exterior walls of the second pair of spacer structures are laterally displaced from the first and second sidewalls of the first conductive gate by a second displacement distance. The second source/drain impurity distribution is introduced into the pair of source/drain regions. The pair of second source/drain regions are laterally displaced on either side of the channel region of the first transistor region. Interior boundaries of the second pair of source/drain regions are laterally displaced from first and second sidewalls of the first conductive gate by the second displacement. The step of forming the gate dielectric comprises thermally oxidizing of the upper surface of the semiconductor substrate at a temperature greater than approximately 800xc2x0 C. for a duration sufficient to produce a thickness of the gate dielectric approximately 20 to 200 angstroms. The formation of the first and second conductive gates may comprise chemically vapor depositing polysilicon or, alternatively, sputter depositing a metal such as aluminum, copper, or tungsten.
In one embodiment, the step of forming the first and second gate insulators comprises thermally oxidizing exposed surfaces including the sidewalls of the first and second conductive gates. In one preferred embodiment, the step of depositing the first spacer dielectric material comprises chemically vapor depositing silicon nitride. The formation of the second pair of dielectric spacers, in one embodiment, may include depositing a second spacer dielectric material on a topography cooperatively defined by the first and second conductive gates. The first and second conductive gates, the first and second gate insulators, and the upper surface of the semiconductor substrate. The deposition of the second spacer dielectric material is preferably accomplished at a pressure less than approximately 2 torrs such that a substantially conformal second spacer dielectric layer is produced. Thereafter, the second spacer dielectric material is anisotropically etched such that portions of the second spacer dielectric material are removed from planar surfaces of the topography. For purposes of this disclosure, a planar surface refers to a surface substantially parallel with the upper surface of the semiconductor substrate. The deposition of the second spacer dielectric material preferably comprises chemical vapor depositing oxide. In one embodiment, the formation of the first and second conductive gate includes the steps of sputter depositing a metal of aluminum, copper, or an alloy thereof onto the gate dielectric and patterning the metal with a photolithography masking step. Ideally, the steps of introducing the various impurity distributions into the semiconductor substrate comprise implanting ions of arsenic, boron or phosphorous. In one such embodiment, an implant dose for the step of introducing the lightly doped impurity distributions into the semiconductor substrate is less than approximately 5xc3x971014 atoms/cm2. A suitable implant dose for the step of introducing the first source/drain impurity distribution into the semiconductor substrate is in the range of approximately 2xc3x971012 to 5xc3x971015 atoms/cm2. A suitable implant dose for the introduction of the second source/drain impurity distribution into the semiconductor substrate is preferably greater than approximately 5xc3x971014 atoms/cm2.